1. Field of the invention
This invention relates to a sampling clock generation circuit for accurately sampling image data assigned to each display and contained in a video signal in a recording apparatus which receives the video signal and records the image data.
2. Description of the Prior Art
Accuracy and resolution of image display devices in recent CAD.CAM applications have been improved, and recording apparatuses used for such applications must reproduce the displayed image with a high level of fidelity. In order to particularly attain high fidelity recording of graphic display by use of video signals as a medium, sampling of the image data by use of clocks on the one-to-one correspondence basis must be ensured for pixels. Since the image data signal of each pixel is in synchronism with a horizontal sync signal as shown in FIG. 6 of the accompanying drawings, the sampling clock must be in synchronism with the horizontal sync signal, too. For this reason, the sampling clock in the conventional apparatuses is generated by an oscillation circuit which oscillates at the same frequency as the video signal, and only the phase is controlled by a PLL circuit using a variable delay circuit with the horizontal sync signal being the reference.
An example of the conventional sampling clock generation circuits will be explained with reference to FIG. 2.
The conventional sampling clock generation circuit consists of a portion which compares the phase of a horizontal sync signal synchronized by a sampling clock with that of a delayed horizontal sync signal and detects the phase difference of the sampling clock with respect to the horizontal sync signal, and a portion which controls the phase of the output signal of an oscillation circuit oscillating at the same frequency as that of a video signal by a variable delay circuit. When the phase advance of the sampling clock is detected, the delay quantity of the variable delay circuit is changed so as to delay the phase of the sampling clock, and when the phase delay of the sampling clock is detected, the delay quantity of the variable delay circuit is changed so as to advance the phase of the sampling clock. In this manner, the sampling clock capable of accurately sampling the image data of each pixel contained in the video signal is generated by adjusting the phase of the sampling clock to that of the horizontal sync signal as the reference.
When the difference of frequency is great between the oscillation frequency of the oscillation circuit and the video signal, the conventional method described above cannot control the phase because the phase is deviated within one horizontal period and accurate sampling cannot be made any longer so that the range of an allowable video signal frequency is narrow, and moreover, a high precision oscillation circuit has been necessary.
Furthermore, since the variable delay circuit selects output signals having different delay quantities of delay elements and changes the delay quantity, the delay quantity can be controlled only discretely. For this reason, the phase error of the sampling clock is great and high precision delay elements have been necessary.
Hence, the conventional method described above is applied to several 10 MHz of video signal frequency at most. On the contrary, higher resolution and multi-color of image display devices in recent CAD.CAM applications have required to deal with over 100 MHz of video signal frequency. Accordingly, the cost has become problem on account of needs of higher precision components.